There is currently two different Header Types, which are Type 1 for bridges, switches and root complexes. The Configuration Space Header provides information to enable the operating system to interact and control the device. The structure of the CONFIG_ADDRESS register can be found below: With the newer mechanism, two 32-bit I/O registers are created, one is called CONFIG_ADDRESS (0xCF8) and is used to provide the configuration address to be accessed, whereas, the second is named CONFIG_DATA and is used to transfer data to and from the CONFIG_DATA register. I mentioned earlier about the two types of Mechanisms used to access the Configuration Space.
This is IRP is also the Minor Function Code for a PnP IRP, and also must be called at IRQL level lower than DISPATCH_LEVEL for the same reasons above. The IRP_MN_READ_CONFIG is used to read data from the configuration space.
#PCIE MEMORY SPACE DRIVER#
Since the buffer containing the information to be written is allocated from paged pool, the bus driver must call this IRP at IRQL lower than DISPATCH_LEVEL. The IRP is a Minor Function Code for a PnP IRP. The IRP_MN_WRITE_CONFIG is used to to write data to the configuration space specified.
#PCIE MEMORY SPACE DRIVERS#
The Configuration Space can be accessed by drivers with a set IRPs, or by accessing members within the BUS_INTERFACE_STANDARD data structure. Mechanism #2 is only provided for backwards compatibility, and therefore will not be part of the discussion later on. This mechanism is divided into two parts: Mechanism #1 and Mechanism #2. Although, in order to make the PCI Configuration Space accessible (most CPUs do not support such access), there must be kind of mechanism, which can allow access to the PCI Configuration Space. The target device for the Configuration Space Access is selected with the Initialization Device Select (IDSEL) signal, which is then decoded by the target device. The Configuration Space is typically 256 bytes, and can be accessed with Read/Write Configuration Cycles. These registers are then mapped to memory locations such as the I/O Address Space of the CPU. The PCI Configuration Space is a set of registers, on PCI Express (PCIe) buses, this configuration space may be referred to as the the Extended Configuration Space.
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